مدل سازی بستر جفت سر و صدا در مخلوط سیگنال مدارهای یکپارچه
Abstract: The continuing need for portability, low power, and low cost is driving the emergence of Systems-on-a-Chip (SoC). A system-on-a-chip is defined as a mixed-technology design, integrating various types of designs on a single chip, such as memory, digital, analog, radio-frequency (RF), and even micro-electro-mechanical systems (MEMS) and optical input/output. A major disadvantage of the SoC technology, however, is the undesirable interaction among components. The interaction can occur through mutual inductance or capacitive coupling between metal interconnects, or through the common substrate. Interaction through the shared substrate is referred to as Substrate Noise Coupling (SNC). Today\'s SoC devices have to accommodate the need for both higher clock frequencies in the digital portions as well as high precision in the analog portions. The noise associated with the fast-switching transients in the digital blocks can couple through the substrate and affect the noise-sensitive nodes in the analog sections. Such coupling leads to voltage fluctuations in the bulk, which in turn affects analog performance. This work enhances understanding of substrate noise mechanisms: its physical origin, generation, transmission, and reception mechanisms. A novel model for predicting voltage fluctuations in the bulk is developed, and design practices for reducing substrate noise coupling are also recommended.